Impact of CMOS Scaling on Single-Event Hard Errors in Space Systems

Applications of highly scaled devices in space applications are shown to be limited by hard errors from cosmic rays. Hard errors were first observed in 0.8 pm DRAMs. For feature sizes below 0.5 ~nl, scaling theory predicts that low power devicees will have much lower hard error rates than devices optimized for high speed. introduction Recent emphasis on low… (More)