Identifying DC bias conditions for maximum DC current in digitally-assisted analog design

@article{Li2015IdentifyingDB,
  title={Identifying DC bias conditions for maximum DC current in digitally-assisted analog design},
  author={Chong Li and Suriyaprakash Natarajan and C.-J. Richard Shi},
  journal={2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)},
  year={2015},
  pages={478-481}
}
We propose a novel methodology for maximizing DC current in digitally-assisted analog circuit. The proposed methodology identifies a set of analog bias voltages and digital mode selection signals that maximizes the DC current through either a particular wire segment or the power/ground bus. This technique enables sensitization of EM related faults. First, a channel-connected graph is built from a mixed signal transistor circuit, then the current activation condition is formulated as… CONTINUE READING

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References

Publications referenced by this paper.
SHOWING 1-9 OF 9 REFERENCES

Framework for analog test coverage

  • International Symposium on Quality Electronic Design (ISQED)
  • 2013
VIEW 1 EXCERPT

Functional Test Selection for High Volume Manufacturing

  • Seventh International Workshop on Microprocessor Test and Verification (MTV'06)
  • 2006
VIEW 1 EXCERPT

Convex Optimization

  • IEEE Transactions on Automatic Control
  • 2004
VIEW 1 EXCERPT

Switch level simulation employing dynamic short-circuit ratio, US Patent: US5703798 A

S. Dhar
  • Dec. 1997.
  • 1997
VIEW 1 EXCERPT

A formulation to optimize stress testing

  • 1994 Proceedings. 44th Electronic Components and Technology Conference
  • 1994
VIEW 1 EXCERPT