Iddt Test Calibration using a Programmable Processing Array

Abstract

This paper proposes an area efficient signal processing architecture to perform IDDT test calibration through vector multiplication. The design follows the Field Programmable Array organization, and capitalizes on the unique behavior of binary encoded signals to implement compact multiply elements. Vectors with 8 bit values were multiplied at a rate of 300… (More)

7 Figures and Tables

Cite this paper

@article{Itskovich2008IddtTC, title={Iddt Test Calibration using a Programmable Processing Array}, author={Michelle Itskovich and Jim Plusquellic}, journal={2008 4th Southern Conference on Programmable Logic}, year={2008}, pages={265-268} }