IS-FPGA : a new symmetric FPGA architecture with implicit scan

  title={IS-FPGA : a new symmetric FPGA architecture with implicit scan},
  author={Michel Renovell and Penelope Faure and Jean Michel Portal and Joan Figueras and Yervant Zorian},
This paper proposes a new and original FPGA architecture with testability facilities. It is first demonstrated that classical FPGA architectures do not allow to efficiently implement sequential circuits with a SCAN chain. It is consequently proposed to modify the architecture of classical FPGAs in order to create an Implicit-Scan chain into the FPGA itself called Implicit Scan FPGA (IS-FPGA). Using this new FPGA architecture, any sequential circuit implemented into the FPGA is ‘implicitly… CONTINUE READING
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