INSERTION TO SPEED-UP LOGIC VERIFICATI 0 N : A RECENT DEVELOPMENT Invited Paper

@inproceedings{PradhanINSERTIONTS,
  title={INSERTION TO SPEED-UP LOGIC VERIFICATI 0 N : A RECENT DEVELOPMENT Invited Paper},
  author={Dhiraj K. Pradhan}
}
Logic verification continues to be considered one of CAD'S most difficult problems, highlighted with the discovery of the Pentium bug dilemma. This talk reviews certain current innovations addressing such problems. A new method will be discussed, based on what has become known as Recursive Learning Technique. This proposed technique has its cornerstone in… CONTINUE READING