• Corpus ID: 212530945

IMPLEMENTATION OF V EDIC M ULTIPLIER USING VHDL CODE

@inproceedings{Vaithiyanathan2013IMPLEMENTATIONOV,
  title={IMPLEMENTATION OF V EDIC M ULTIPLIER USING VHDL CODE},
  author={G. Vaithiyanathan and Kalaichelvi Venkatesan and S. Sivaramakrishnan and Shrihari Siva and Selvakumar Jayakumar},
  year={2013}
}
In a typical processor, Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multipliers. In computers, a typical central processing unit devotes a considerable amount of processing time in implementing arithmetic operations, particularly multiplication operations .In this project , the comparative study of different… 

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References

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An algorithm to achieve fast multiplication in two's complement representation is presented, which results in a true diamond-shape for the partial product tree, which is more efficient in terms of implementation.

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