III-V gate-all-around nanowire MOSFET process technology: From 3D to 4D

@article{Gu2012IIIVGN,
  title={III-V gate-all-around nanowire MOSFET process technology: From 3D to 4D},
  author={J. J. Gu and Xianyan Wang and Jiayi Shao and Adam T. Neal and Michael J. Manfra and R. G. Gordon and P. D. Ye},
  journal={2012 International Electron Devices Meeting},
  year={2012},
  pages={23.7.1-23.7.4}
}
In this paper, we have experimentally demonstrated, for the first time, III-V 4D transistors with vertically stacked InGaAs nanowire (NW) channels and gate-all-around (GAA) architecture. Novel process technology enabling the transition from 3D to 4D structure has been developed and summarized. The successful fabrication of InGaAs lateral and vertical NW arrays has led to 4× increase in MOSFET drive current. The top-down technology developed in this paper has opened a viable pathway towards… CONTINUE READING
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