IOoQ techniques have been widely used at Intel over the past years to (a) successfully improve outgoing quality ofthe products by screening defects early in production testing, (6) eliminate or reduce Burn In, and (c) improve overall fault grading. Functional (Non-scan) IDDO testing has been implemented successfully on a number of products (i9608, i386rMM, and MCSB micro-controllers). With more designs implementing Scan, the capability to select, grade and implement Scan--based IoDQ vectors and the resulting contribution to the overall fault coverage can be complicated. Using this IooO test methodology, we show how to (a) integrate test techniques into the design jlow, (b) eliminate the need for fault grading, (c) use ScadDDQ to improve fault coverage, and (4 determine the incremental Nonscan and Scan IDDQ coverage impact to the full chip. This paper details the new test technique, methodology, flows, tradeoffbenefits, implementation, and results for IDDO vector generation, grading, selection and testing of vectors for Non-Scan and Scan--based designs. This technique allows user(s) the option of eliminating comprehensive fault grading resources, and uses existing or new Electronic Design Automation (EDA) tools to achieve desired quality levels prior to design completion, and production testing. Introduction Today Computing Enhancement Group (CEG) uses an internal IODQ tool set for vector selection, grading, and for merging the leakage and Stuck faults detected by IDDQ and Zycad* (referred subsequently as Zycad) respectively [ 6 ] . This process takes from 4 to 6 weeks (min) and upto 8 weeks (or more) for most large scale designs (> 1 million transistors). The I, processor tool input is a list of all faults detected by IDW and Zycad. This tool calculates the additional Zycad S@F coverage contributed by the IDW strobe points. It removes any overlapping detected faults against the Zycad fault simulation “fault origin file (.fog)”. The non overlapping detects found by the IDDQ strobe point evaluated is then added into the Zycad fault origin tile for the module it was targeted. There are several key limitations associated with this approach: (a) accurately identifying how many of the previously undetected and possible detects are considered detected by I, testing, (b) timing of where unique faults are merged with simulation data, (c) the efficiency of the tool and methodology, and (d) supports more Non-scan designs or limited Scan--based designs. Therefore, we ran numerous test cases, design fubs and full chip designs, through the current IDDQ tool and a scan based combinational Pseudo Stuck At Fault (PSAF) model tool to evaluate the IoDQ process for vector generation, grading and selection. We compared and established tradeoffs, for vector grading and selection to further provide for an optimized test methodology, flow and I, testing for both Non-Scan and Scan designs.