Hybrid design of dual Vth and power gating to reduce leakage power under Vth variations

Increase in leakage power and Vth variation is a critical concern in leading-edge CMOS technology. Traditional dual Vth design with the worst corner model becomes difficult to achieve for low leakage because delay variation of high Vth cell is increased significantly by Vth variation. In this paper, we demonstrated that a power gated cell is more tolerant… CONTINUE READING