Hybrid Leakage and Voltage Reduction under EDF Scheduling


Recent trends in CMOS fabrication have resulted in an increasing need to conserve power of processors. While dynamic voltage scaling (DVS) is effective in reducing dynamic power, the latest dies are increasingly dominated by static power. For such processors, voltage/frequency pairs below a critical speed result in higher power consumption than entering a… (More)


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@inproceedings{ZhuHybridLA, title={Hybrid Leakage and Voltage Reduction under EDF Scheduling}, author={Yifan Zhu and Frank M{\"u}ller} }