How significant will be the test cost share for 3D die-to-wafer stacked-ICs?

@article{Taouil2011HowSW,
  title={How significant will be the test cost share for 3D die-to-wafer stacked-ICs?},
  author={Mottaqiallah Taouil and Said Hamdioui and Erik Jan Marinissen},
  journal={2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)},
  year={2011},
  pages={1-6}
}
Several challenges must be overcome before high volume production of the 3D Stacked-ICs (3D-SIC) can be realized. A key challenge is to guarantee the required product quality at minimal overall cost. Testing, which is an integral part of 3D-IC manufacturing, should be performed in such way that its cost contribution is optimal. This paper investigates the impact of different test moments for pre-bond and post-bond stacks (resulting into different test flows) on the overall cost of die-to-wafer… CONTINUE READING