Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications

@article{Brisbin2002HotCR,
  title={Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications},
  author={Douglas Brisbin and Andy Strachan and Prasad Chaparala},
  journal={2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320)},
  year={2002},
  pages={105-110}
}
  • D. Brisbin, A. Strachan, P. Chaparala
  • Published 7 August 2002
  • Engineering
  • 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320)
This paper evaluates the hot carrier performance of n-channel lateral DMOS (N-LDMOS) transistors. The N-LDMOS has been the common choice for the driver transistor in high voltage (20-30 V) smart power applications. These high drain voltages potentially make N-LDMOS hot carrier degradation an important reliability concern. This paper focuses on the hot carrier test methodology and geometry effects in N-LDMOS transistor arrays. This paper differs from previous work in that it describes for the… 
Effect of Photo Misalignment on N-LDMOS Hot Carrier Device Reliability
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Photo Misalignment Impact on the Hot Carrier Reliability of Lateral DMOS Devices
Power management devices often require operation in the 20 V to 30 V range. A common choice for the power MOS driver is an n-channel lateral DMOS (N-LDMOS) device. An advantage of N-LDMOS device is
1-D and 2-D hot carrier layout optimization of N-LDMOS transistor arrays
Today's power management devices often require operation in the 20-30 V range. These applications often combine a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain
Hot carrier degradation in LDMOS power transistors
The hot carrier performance of N-LDMOS and P-LDMOS transistors is evaluated. For N-LDMOS transistors, the drain current degradation is shown to be due to hot electron injection in the drift region
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Automotive and telecom applications often require voltages in the 20-30V range. These circuits combine high performance CMOS with a high voltage MOS transistor. A possible choice for the high voltage
Effects of Drift-Region Design on the Reliability of Integrated High-Voltage LDMOS Transistors
Effects of drift-region design on the hot-carrier reliability of n-channel integrated high-voltage lateral diffused MOS (LDMOS) transistors are investigated. LDMOS devices with various dosages of
Measurement and characterization of hot carrier safe operating area (HCI-SOA) in 24V n-type lateral DMOS transistors
TLDR
This paper will focus on the HCI-SOA test methodology and characterization for n-type LDMOS device by adopting the conventional CMOS HCI test method, which will be a useful guideline for the industry on the device characterization process.
Anomalous Safe Operating Area and Hot Carrier Degradation of NLDMOS Devices
Automotive and telecom applications often require voltages in the 20-30 V range. These circuits combine high-performance CMOS with a high-voltage MOS transistor. A possible choice for the
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