Horus: large-scale symmetric multiprocessing for Opteron systems

@article{Kota2005HorusLS,
  title={Horus: large-scale symmetric multiprocessing for Opteron systems},
  author={Rajesh Kota and Rich Oehler},
  journal={IEEE Micro},
  year={2005},
  volume={25},
  pages={30-40}
}
Horus lets server vendors design up to 32-way Opteron systems. Horus is the only chip that targets the Opteron in an SMP implementation. By implementing a local directory structure to filter unnecessary probes and by offering 64 Mbytes of remote data cache, the chip significantly reduces overall system traffic as well as the latency for a coherent hypertransport transaction. 
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Horus: Large-Scale SMP for Opteron,

R. Oehler, R. Kota
2004
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