Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory

@article{Leonov2015HoldInPA,
  title={Hold-In, Pull-In, and Lock-In Ranges of PLL Circuits: Rigorous Mathematical Definitions and Limitations of Classical Theory},
  author={Gennady A. Leonov and Nikolay V. Kuznetsov and Marat V. Yuldashev and Renat V. Yuldashev},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2015},
  volume={62},
  pages={2454-2464}
}
The terms hold-in, pull-in (capture), and lock-in ranges are widely used by engineers for the concepts of frequency deviation ranges within which PLL-based circuits can achieve lock under various additional conditions. Usually only non-strict definitions are given for these concepts in engineering literature. After many years of their usage, F. Gardner in the 2nd edition of his well-known work, Phaselock Techniques, wrote “There is no natural way to define exactly any unique lock-in frequency… 
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