Highly-scalable 3D CLOS NOC for many-core CMPs

  title={Highly-scalable 3D CLOS NOC for many-core CMPs},
  author={Aamir Zia and Sachhidh Kannan and Garrett Robert Rose and H. Jonathan Chao},
  journal={Proceedings of the 8th IEEE International NEWCAS Conference 2010},
In order to accommodate hundreds of processing elements forming many-core chip multiprocessors (CMP), there is a growing need for easily scalable, high-performance and low-power interconnect infrastructure. In this paper, we propose using 3D integrated CLOS network-on-chip (CNOC) to achieve these goals. We present the design of a 512-node 3D CNOC and evaluate its power consumption. We compare the power consumption of 3D CNOC with a planar CNOC implementation and with 2D and 3D mesh topologies. 
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