Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU

@article{Noguchi2014HighlyRA,
  title={Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU},
  author={Hiroki Noguchi and Kazutaka Ikegami and Naoharu Shimomura and Tetsufumi Tanamoto and Junichi Ito and Shinobu Fujita},
  journal={2014 Symposium on VLSI Circuits Digest of Technical Papers},
  year={2014},
  pages={1-2}
}
This paper presents a novel nonvolatile last level cache (LLC) based on the advanced perpendicular STT-MRAM to reduce the total power consumption of LLC. The presented LLC has novel readout circuit with the dual-sensing salvation scheme that enhances reliability of STT-MRAM along with typical error-correcting code (ECC). The comparison of CPU performance per power with SRAM-based, embedded DRAM and conventional STT-MRAM-based LLCs indicates that the presented novel nonvolatile LLC is the most… CONTINUE READING
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