High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding

@inproceedings{Lee2010HighthroughputLV,
  title={High-throughput low-cost VLSI architecture for AVC/H.264 CAVLC decoding},
  author={Gwo Giun Lee and Chia-Cheng Lo and Ya-ping Chen and Hung-Yin Lin and Mark C.H. Wang},
  year={2010}
}
This study develops a low-cost very-large-scale-integration (VLSI) hardware architecture for entropy coding with increased throughput using the statistical properties of context-based adaptive variable-length coding (CAVLC) in AVC/H.264. Statistical analyses show that better symbol length prediction was achieved by breaking the recursive dependency among codewords for the multi-symbol decoder implementation. The proposed CAVLC decoder easily meets the real-time requirements for high definition… CONTINUE READING

Figures, Tables, Results, and Topics from this paper.

Key Quantitative Results

  • The proposed architecture design reduces processing cycles by 23% compared to Yu’s design with little area cost, because a codeword length prediction circuit and three RunBefore decoders are adopted in our design.

Citations

Publications citing this paper.
SHOWING 1-7 OF 7 CITATIONS

A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video

  • IEEE Transactions on Circuits and Systems for Video Technology
  • 2012
VIEW 4 EXCERPTS
CITES BACKGROUND
HIGHLY INFLUENCED

Architecture of high-throughput context adaptive variable length coding decoder in AVC/H.264

  • Proceedings of The 2012 Asia Pacific Signal and Information Processing Association Annual Summit and Conference
  • 2012

References

Publications referenced by this paper.
SHOWING 1-10 OF 26 REFERENCES

A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding

  • 2005 IEEE International Symposium on Circuits and Systems
  • 2005
VIEW 8 EXCERPTS
HIGHLY INFLUENTIAL

A novel design of CAVLC decoder with low power consideration

  • 2007 IEEE Asian Solid-State Circuits Conference
  • 2007
VIEW 4 EXCERPTS
HIGHLY INFLUENTIAL

High Performance VLSI Architecture Design for H.264 CAVLC Decoder

  • IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
  • 2006
VIEW 4 EXCERPTS
HIGHLY INFLUENTIAL

A VLSI architecture design of CAVLC decoder

VIEW 3 EXCERPTS
HIGHLY INFLUENTIAL

AVC/H.264 baseline profile decoder optimization on independent platform

Q. XUE, J. LIU, S. WANG, J. ZHAO
  • Int. Conf. IET Image Process.,
  • 2010
VIEW 1 EXCERPT

Efficient VLSI design for data transformations of tree-based codes

A. MUKHERJEE, N. RANGANATHAN, M. BASSIOUNI
  • IEEE Trans. Circuits Syst., 1991,
  • 2010

Design of high - speed CAVLC decoder architecture for AVC / H . 264

W. CHENT., W. HUANGY., +3 authors G. CHENL.
  • 2008

A Pattern-Search Method for H.264/AVC CAVLC Decoding

  • 2006 IEEE International Conference on Multimedia and Expo
  • 2006
VIEW 1 EXCERPT

A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264

  • 2006 IEEE International Symposium on Circuits and Systems
  • 2006
VIEW 3 EXCERPTS