High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2m)

@article{Meher2007HighthroughputHD,
  title={High-throughput hardware-efficient digit-serial architecture for field multiplication over GF(2m)},
  author={P. Meher},
  journal={2007 6th International Conference on Information, Communications & Signal Processing},
  year={2007},
  pages={1-5}
}
  • P. Meher
  • Published 2007 in
    2007 6th International Conference on Information…
It presents a novel digit-serial architecture for finite field multiplications over GF(2m) defined by irreducible trinomials as field polynomials. The critical path of the proposed structure is reduced, and a saving of m number of XOR gates is achieved by the proposed structure at the final output stage by successive finite field accumulation through T flip… CONTINUE READING