High throughput hardware architecture for accurate semi-global matching

Abstract

As the most important step of a stereo vision system, stereo matching, which finds the correspondences in stereo image pairs, requires high-quality real-time depth computation. In this paper, a high accuracy and high throughput full-pipeline hardware architecture with disparity and row parallelism is proposed. In the semi-global aggregation stage, to improve the accuracy in discontinuous regions, adaptive weighted path costs are adopted, and, five aggregation paths are used without consuming external memory resources. The proposed hardware architecture is implemented on a Stratix V FPGA, which results in a throughput of 1280×960/197fps with 64 disparity levels at 156MHz.

DOI: 10.1109/ASPDAC.2017.7858396

9 Figures and Tables

Cite this paper

@article{Li2017HighTH, title={High throughput hardware architecture for accurate semi-global matching}, author={Yan Li and Chen Yang and Wei Zhong and Zhiwei Li and Song Chen}, journal={2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC)}, year={2017}, pages={641-646} }