High-throughput decoder for low-density parity-check code

@article{Ishikawa2006HighthroughputDF,
  title={High-throughput decoder for low-density parity-check code},
  author={Tatsuyuki Ishikawa and Kazunori Shimizu and Takeshi Ikenaga and Satoshi Goto},
  journal={Asia and South Pacific Conference on Design Automation, 2006.},
  year={2006},
  pages={2 pp.-}
}
We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304bit regular LDPC codes using modified min-sum algorithm. The decoder achieves a throughput of 530Mb/s at an operating frequency of 147MHz. The chip has been fabricated in a 0.18μm, 6 metal-layer CMOS technology. The chip size is 36mm2. 

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