High throughput architecture for high performance NoC

  title={High throughput architecture for high performance NoC},
  author={Mohamed A. Abd El-Ghany and Magdy A. El-Moursy and Mohammed Ismail},
  journal={2009 IEEE International Symposium on Circuits and Systems},
High Throughput Butterfly Fat Tree (HTBFT) architecture to achieve high performance Networks on Chip (NoC) is proposed. The architecture increases the throughput of the network by 38% while preserving the average latency. The area of HTBFT switch is decreased by 18% as compared to Butterfly Fat Tree switch. The total metal resources required to implement HTBFT design is increased by 5% as compared to the total metal resources required to implement BFT design. The extra power consumption… CONTINUE READING


Publications citing this paper.


Publications referenced by this paper.
Showing 1-10 of 31 references

On network-on-chip comparison

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007) • 2007

Testing Network-on-Chip Communication Fabrics

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems • 2007

Towards Open Network-on-Chip Benchmarks

First International Symposium on Networks-on-Chip (NOCS'07) • 2007

Increasing the throughput of an adaptive router in network-on-chip (NoC)

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06) • 2006
View 1 Excerpt

Low-power network-on-chip for high-performance SoC design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems • 2006
View 1 Excerpt

Similar Papers

Loading similar papers…