High speed pipeline architecture for adaptive median filter


In low level data processing functions, like FIR filtering, pattern recognition or correlation, where the parallel implementation is supported by architecture matched special purpose arithmetic; high throughput FPGA circuits easily outperform even the most advanced DSP processors. This paper investigates a high-speed, non-linear adaptive median filter implementation. Adaptive median filter solves the dual purpose of removing the impulse noise and reducing distortion in the image. It can achieve the filtering operation of an image corrupted with impulse noise of probability greater than 0.2.

DOI: 10.1145/1523103.1523223

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@inproceedings{Dhanasekaran2009HighSP, title={High speed pipeline architecture for adaptive median filter}, author={Duraisamy Dhanasekaran and Akilesh Krishnamurthy and J. Ramkumar}, booktitle={ICAC3 '09}, year={2009} }