High-speed monolithic CMOS limiting amplifier with low-pass network

Abstract

To achieve wide-bandwidth performance, this paper proposes an on-chip high-speed limiting amplifier that employs a low-pass network topology. To avoid the parasitic effects of the on-chip spiral inductor, several short circuit coplanar stripline stubs fabricated with thicker top metal layer are used as passive inductors. The gain and bandwidth of the… (More)

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Cite this paper

@article{Fuhua2005HighspeedMC, title={High-speed monolithic CMOS limiting amplifier with low-pass network}, author={Li Fuhua and Huang Qiuping and Qian Min}, journal={Proceedings of 2005 IEEE International Workshop on VLSI Design and Video Technology, 2005.}, year={2005}, pages={14-16} }