High-speed hardware architectures of the Whirlpool hash function

@article{ONeill2005HighspeedHA,
  title={High-speed hardware architectures of the Whirlpool hash function},
  author={M{\'a}ire O'Neill and Ciaran McIvor and Aidan Savage},
  journal={Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.},
  year={2005},
  pages={147-153}
}
  • M. O'Neill, C. McIvor, Aidan Savage
  • Published 11 December 2005
  • Computer Science
  • Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.
High-speed hardware architectures of the Whirlpool hash function are presented in this paper. A full look-up table (LUT) based design is shown to be the fastest method by which to implement the non-linear layer of the algorithm in terms of logic. An iterative Whirlpool architecture implemented on the Virtex X4VLX100 device runs at 4.79 Gbps, while an unrolled architecture achieves a throughput of 4.9 Gbps. This is faster than a SHA-512 design implemented on the same device and other previously… 

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