Corpus ID: 55232409

High speed gate level synchronous full adder designs

@article{Balasubramanian2009HighSG,
  title={High speed gate level synchronous full adder designs},
  author={P. Balasubramanian and N. Mastorakis},
  journal={WSEAS Transactions on Circuits and Systems archive},
  year={2009},
  volume={8},
  pages={290-300}
}
  • P. Balasubramanian, N. Mastorakis
  • Published 2009
  • Engineering
  • WSEAS Transactions on Circuits and Systems archive
  • Addition forms the basis of digital computer systems. Three novel gate level full adder designs, based on the elements of a standard cell library are presented in this work: one design involving XNOR and multiplexer gates (XNM), another design utilizing XNOR, AND, Inverter, multiplexer and complex gates (XNAIMC) and the third design incorporating XOR, AND and complex gates (XAC). Comparisons have been performed with many other existing gate level full adder realizations. Based on extensive… CONTINUE READING
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