• Corpus ID: 55232409

High speed gate level synchronous full adder designs

@article{Balasubramanian2009HighSG,
  title={High speed gate level synchronous full adder designs},
  author={Padmanabhan Balasubramanian and Nikos E. Mastorakis},
  journal={WSEAS Transactions on Circuits and Systems archive},
  year={2009},
  volume={8},
  pages={290-300}
}
Addition forms the basis of digital computer systems. Three novel gate level full adder designs, based on the elements of a standard cell library are presented in this work: one design involving XNOR and multiplexer gates (XNM), another design utilizing XNOR, AND, Inverter, multiplexer and complex gates (XNAIMC) and the third design incorporating XOR, AND and complex gates (XAC). Comparisons have been performed with many other existing gate level full adder realizations. Based on extensive… 

A delay improved gate level full adder design

TLDR
Comprehensive comparison with similar implementations encompassing only different gate level full adder designs further substantiate the speed efficiency of the proposed adder, all targeting the highest speed corner of the 65nm STMicroelectronics CMOS process.

A low power gate level full adder module

TLDR
The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP) even in comparison with the fullAdder element that has been made available as part of two commercial standard cell libraries.

Fast Mux-based Adder with Low Delay and Low PDP

TLDR
Synthesis results show that the proposed 16 and 32-bit adders have the lowest computation delay and also the best power delay product (PDP) among all recent popular adders.

FPGA-Based Synthesis of High-Speed Hybrid Carry Select Adders

TLDR
In this work, two new hybrid carry select adders are proposed involving the carry select and section-carry based carry lookahead subadders with/without binary to excess 1 converters.

Implementation of an XOR Based 16-bit Carry Select Adder for Area, Delay and Power Minimization

  • A. HossainM. Abedin
  • Computer Science, Engineering
    2019 International Conference on Electrical, Computer and Communication Engineering (ECCE)
  • 2019
TLDR
The modified 16-bit carry select adder is presented using modified XOR based full adder to reduce circuit complexity, area and delay and gives better result than conventional carry selectAdder with respect to area, power consumption and delay.

64bit Hybrid Adder for ALU Design Applications

  • Computer Science
    International Journal of Innovative Technology and Exploring Engineering
  • 2020
TLDR
A proposed model of a 64bit hybrid adder optimized all aspects of the model while increasing the speed of the device.

Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

TLDR
A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology and simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench.

Comparison of 14 Different Gate Level 1-bit Full Adder Design at Constant Delay

TLDR
A trade-off among different parameters like Area acquired, Power used, Quality & Performance (PDP), Energy efficiencies (EDP) of fourteen different full adder circuit is calculated and analyzed at 90nm CMOS technology on DSCH 3.8 software.

LOW AREA HIGH SPEED COMBINED MULTIPLIER USING MULTIPLEXER BASED FULL ADDER

TLDR
The Shannon full adder circuit based multiplier circuits gives better performance than other published results in terms of power dissipation and area due to less number of transistors used in Shannon adder.

Performance Comparison of some Synchronous Adders

TLDR
This technical note compares the performance of some synchronous adders which correspond to the following architectures and finds the hybrid CCLA-RCA is preferable to the other adders in terms of the speed, the power-delay product, and the energy- delay product.

References

SHOWING 1-10 OF 12 REFERENCES

On the design of low-energy hybrid CMOS 1-bit full adder cells

TLDR
Several designs for 1-bit full adder cell featuring hybrid CMOS logic style based on a novel XOR-XNOR circuit that simultaneously produces XOR and XNOR full-swing outputs and outperforms its best counterpart showing 39% improvement in PDP.

A novel multiplexer-based low-power full adder

TLDR
A novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T) that has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption.

Design of a low-power, high performance, 8×8 bit multiplier using a Shannon-based adder cell

Performance analysis of low-power 1-bit CMOS full adder cells

TLDR
A performance analysis of 1-bit full-adder cell is presented, after the adder cell is anatomized into smaller modules, and several designs of each of them are developed, prototyped, simulated and analyzed.

Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

TLDR
The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability and is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously.

A novel hybrid pass logic with static CMOS output drive full-adder cell

TLDR
A novel design of a 1-bit full adder cell featuring a hybrid CMOS logic style is proposed, which is very power efficient and has lower power-delay product over a wide range of voltages.

A novel low power energy recovery full adder cell

TLDR
The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder.

CMOS Logic Circuit Design

TLDR
CMOS Logic Circuit Design is an up-to-date treatment of the analysis and design of CMOS integrated digital logic circuits that covers all of the important digital circuit design styles found in modern CMOS chips.

A new design of the CMOS full adder

TLDR
By using the transmission function theory, two CMOS full adders are designed, both of which have simpler circuits than the conventional full adder, and they have desirable transfer characteristics.