# High speed and area efficient vedic multiplier

@article{Kunchigi2012HighSA, title={High speed and area efficient vedic multiplier}, author={V. Kunchigi and L. Kulkarni and S. Kulkarni}, journal={2012 International Conference on Devices, Circuits and Systems (ICDCS)}, year={2012}, pages={360-364} }

High speed pipelined multiplier architecture is proposed in this paper. The pipelined architecture consists of 3 stages. 1st stage consists of the 4 - bit Vedic Multiplication unit. 2nd stage consists of partial products and carry. 3rd stage consists of adders and the result of the multiplication. This paper presents the efficiency of Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of… Expand

#### 75 Citations

LOW POWER ALU DESIGN BY 32 BIT MULTIPLIER VEDIC MULTIPLIER

- 2019

This paper presents Multiply and Accumulate (MAC) unit design using Vedic Multiplier, which is based on Urdhva Tiryagbhyam Sutra. The paper emphasizes an efficient 32-bit MAC architecture along with… Expand

Vedic Multiplier Algorithm to Design 32-bit MAC

- 2014

This paper presents multiply and Accumulate (MAC) unit design using Vedic Multiplier, which is based on Urdhva Tiryagbhyam Sutra. The paper emphasizes an efficient 32-bit MAC architecture along with… Expand

32-BIT MAC UNIT DESIGN USING VEDIC MULTIPLIER

- Computer Science
- 2013

Though the use of Vedic mathematics methods for multiplication is reported in literature, it has been observed that the proposed method of 32-bit MAC unit implementation is using (32X32) multiplication unit and shows improvements in the delay and area. Expand

High speed Vedic multiplier design and implementation on FPGA

- Computer Science
- 2015

Compressor based Vedic Multipliers show considerable improvements in speed and area efficiency. Expand

An Efficient Architecture of Vedic Multiplier using FinFet Based Pass Transistor Logic

- 2020

Multiplies is an important component in Digital Signal Processing (DSP) and communication systems. It is utilized in signal and image processing applications including convolution, Fast Fourier… Expand

FPGA design, simulation and prototyping of a high speed 32-bit pipeline multiplier based on Vedic mathematics

- Computer Science
- IEICE Electron. Express
- 2015

It has been assessed that the multiplier produces partial products by utilizing Vedic mathematics concept by deploying basic 4 × 4 multipliers, which is designed by exploiting special features of multiplexers and 6-input look up tables (LUTs) on the same slices, resulting in considerable minimization in area. Expand

Studies and Performance Evaluation of Vedic Multiplier using Fast Adders

- Computer Science
- 2014

The Vedic Multiplier is designed by Urdhva Tiryagbhyam (UT) technique, constructed with different fast adders and analyzed with FPGA using Xilinx Synthesis Tool (XST). Expand

FPGA Implementation of Multiplier-Accumulator Unit using Vedic multiplier and Reversible gates

- Computer Science
- 2019 Third International Conference on Inventive Systems and Control (ICISC)
- 2019

It has been proved that the proposed DKG gate with Vedic multiplier-adder is having the high speed of operation. Expand

A novel high-speed approach for 16 × 16 Vedic multiplication with compressor adders

- Mathematics, Computer Science
- Comput. Electr. Eng.
- 2016

A novel architecture of Vedic multiplier with 'Urdhava-tiryakbhyam' methodology for 16 bit multiplier and multiplicand is proposed with the use of compressor adders and shows good speed results over Traditional multiplier. Expand

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