High speed and area efficient vedic multiplier

@article{Kunchigi2012HighSA,
  title={High speed and area efficient vedic multiplier},
  author={Vaijyanath Kunchigi and Linganagouda Kulkarni and Subhash Kulkarni},
  journal={2012 International Conference on Devices, Circuits and Systems (ICDCS)},
  year={2012},
  pages={360-364}
}
High speed pipelined multiplier architecture is proposed in this paper. The pipelined architecture consists of 3 stages. 1st stage consists of the 4 - bit Vedic Multiplication unit. 2nd stage consists of partial products and carry. 3rd stage consists of adders and the result of the multiplication. This paper presents the efficiency of Urdhva Triyagbhyam Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of… Expand

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