Corpus ID: 215979251

High speed Vedic multiplier design and implementation on FPGA

@article{Pawale2015HighSV,
  title={High speed Vedic multiplier design and implementation on FPGA},
  author={Prashant D. Pawale and V. Ghodke},
  journal={International journal of applied research},
  year={2015},
  volume={1},
  pages={239-244}
}
In high speed digital signal processing units arithmetic logic units, multiplier and accumulate units, the multipliers are use as the key block. By increasing constraints on delay, more and more emphasis is being laid on design of faster multiplications. For high speed applications, a huge number of adders or compressors are to be used in multiplications to perform the partial product addition. The Array multiplier, Vedic 4*4 multiplier and 8*8 multiplier are designed, then 16*16 multiplier… Expand
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