High speed CML latch using active inductor in 0.18μm CMOS technology

@article{Payandehnia2011HighSC,
  title={High speed CML latch using active inductor in 0.18μm CMOS technology},
  author={Pedram Payandehnia and Hamidreza Maghami and Samad Sheikhaei and Aliazam Abbasfar and Behjat Forouzandeh and Kambiz Nanbakhsh},
  journal={2011 19th Iranian Conference on Electrical Engineering},
  year={2011},
  pages={1-4}
}
In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise. Fortunately, these drawbacks can be tolerated in a shunt peaking CML latch. In addition to cost… CONTINUE READING

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