High speed CML latch using active inductor in 0.18μm CMOS technology

  title={High speed CML latch using active inductor in 0.18μm CMOS technology},
  author={Pedram Payandehnia and Hamidreza Maghami and Samad Sheikhaei and Aliazam Abbasfar and Behjat Forouzandeh and Kambiz Nanbakhsh},
  journal={2011 19th Iranian Conference on Electrical Engineering},
In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise. Fortunately, these drawbacks can be tolerated in a shunt peaking CML latch. In addition to cost… CONTINUE READING


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Publications referenced by this paper.
Showing 1-6 of 6 references

The Design Of CMOS Radio-Frequency Integrated Circuits, 2 Edition

T. H. Lee
View 4 Excerpts
Highly Influenced

Application of Active Inductors in High-Speed I/O Circuits

Y.-S.M. Lee
M.A.Sc. thesis, University of British Columbia, 2006. • 2006
View 3 Excerpts
Highly Influenced

The Role of PLLs in Future Wireline Transmitters

IEEE Transactions on Circuits and Systems I: Regular Papers • 2009
View 1 Excerpt

A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors

2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512) • 2004
View 1 Excerpt

A 27mW 3.6Gb/s I/O transceiver

J.K.L. Wong, H. Hatamkhani, M. Mansuri, K.C.K. Yang
IEEE Journal of Solid-State Circuits, no. 39, pp. 602–612, Apr. 2004. • 2004
View 1 Excerpt

A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers

IEEE Journal of Solid-State Circuits • 2000
View 1 Excerpt

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