High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering

@article{Chan2003HighS4,
  title={High speed 45nm gate length CMOSFETs integrated into a 90nm bulk technology incorporating strain engineering},
  author={V. Chan and Rengasamy Lakhsminarayanan Rengarajan and Nivo Rovedo and W. L. Jin and T. B. Hook and P. Nguyen and Jia Jie Chen and E. J. Nowak and X. Chen and D. Lea and Arnab Chakravarti and Vivian Ku and Shenzhi Yang and A. Steegen and C. Baiocco and Padraic Shafer and Hung Y. Ng and Shih-Fen Huang and C. Wann},
  journal={IEEE International Electron Devices Meeting 2003},
  year={2003},
  pages={3.8.1-3.8.4}
}
A leading edge 90 nm logic bulk foundry technology with 45 nm gate length devices, incorporating strain engineering, is described in this paper. Gate length and dielectric scaling, along with optimized strain engineering, enable high performance devices, which are amongst the best reported to date. Short channel effect control down to 35 nm is demonstrated. Both NMOS and PMOS performance are improved through careful optimization of stress effects from both trench isolation and contact etch stop… CONTINUE READING
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