# High-radix modular multiplication for cryptosystems

@article{Kornerup1993HighradixMM, title={High-radix modular multiplication for cryptosystems}, author={Peter Kornerup}, journal={Proceedings of IEEE 11th Symposium on Computer Arithmetic}, year={1993}, pages={277-283} }

Two algorithms for modular multiplication with very large moduli are analyzed specifically for their applicability when a high radix is used for the multiplier. Both algorithms perform modulo reductions interleaved with the addition of partial products; one algorithm is using the standard residue system, whereas the other utilizes a nonstandard system using reductions modulo a power of the base. The emphasis is on situations, as in cryptosystems, where modular exponentiation is to be realized…

## 70 Citations

New iterative algorithms and architectures of modular multiplication for cryptography

- Computer ScienceICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)
- 2001

The implementation of these algorithms yields to scalable architectures that can be used for any modulus without altering the design, and the Radix-2 algorithm shows almost similar features when compared with similar architectures available in the literature.

High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem

- Computer Science, MathematicsICISC
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This paper presents a high-speed RSA crypto-processor with modified radix-4 Montgomery multiplication algorithm and Chinese Remainder Theorem, which is essential for calculating the Montgomery mapping constant and the modularly reduced ciphertext in CRT technique.

A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem

- Computer ScienceISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349)
- 1999

A high-radix modular multiplication algorithm and its corresponding VLSI architecture for RSA cryptosystem is presented and it is shown how to simplify the quotient estimation based on multiple-bit overlapping scanning and to reduce the logic depth in high- Radix implementation.

Modular exponentiation using parallel multipliers

- Computer Science, MathematicsProceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)
- 2003

A field programmable gate array (FPGA) semi-systolic implementation of a modular exponentiation unit, suitable for use in implementing the RSA public key cryptosystem is presented. The design is…

Title : Rapid Hardware Implementations of Classical Modular Multiplication

- Computer Science
- 2012

This thesis examines the problem of speeding up modular multiplication of large numbers in hardware, using the classical (add-and-shift) multiplication algorithm, and shows that it is possible to pipeline the modular reduction sequence, effectively eliminating the cycle time's dependence on either the size of the modulus, or on the size the radius.

Simplifying quotient determination in high-radix modular multiplication

- Computer ScienceProceedings of the 12th Symposium on Computer Arithmetic
- 1995

Algorithms that are obtained through rewriting of Montgomery's algorithm are presented, where the determination of quotients becomes trivial and the cycle time becomes independent of the choice of radix.

Design and implementation of a coprocessor for cryptography applications

- Computer Science, MathematicsProceedings European Design and Test Conference. ED & TC 97
- 1997

An ASIC suitable for cryptography applications based on modular arithmetic techniques, which works as a coprocessor with a special set of instructions specialized in dealing with high accuracy integers, as well as on the rapid evaluation of modular multiplications and exponentiations.

Dual-field multiplier architecture for cryptographic applications

- Computer Science, MathematicsThe Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003
- 2003

A new hardware architecture is proposed for fast and efficient execution of the multiplication operation in finite fields GF(p) and GF(2/sup n/) and can handle operands of any size; only limited by input/output and scratch space size, not by computational unit.

High-Throughput Modular Multiplication and Exponentiation Algorithms Using Multibit-Scan–Multibit-Shift Technique

- Computer Science, MathematicsIEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 2015

A new and efficient Montgomery modular multiplication architecture based on a new digit serial computation that relaxes the high-radix partial multiplication to a binary multiplication and performs several multiplications of consecutive zero bits in one clock cycle instead of several clock cycles is presented.

A Variable-Radix Systolic Montgomery Multiplier

- Computer Science

A variable radix systolic Montgomery multiplier, suitable for use in implementing the RSA public key cryptosystem is presented. Measurements of the effect of increasing radix on area and performance…

## References

SHOWING 1-10 OF 14 REFERENCES

A high-radix hardware algorithm for calculating the exponential M/sup E/ modulo N

- Computer Science[1991] Proceedings 10th IEEE Symposium on Computer Arithmetic
- 1991

The authors present a parallel version of a well-known exponentiation algorithm that halves the worst-case computing time and describes how a high radix modulo multiplication can be implemented by interleaving a serial-parallel multiplication scheme with an SRT division scheme.

A new carry-free division algorithm and its application to a single-chip 1024-b RSA processor

- Computer Science
- 1989

A carry-free division algorithm is described. It is based on the properties of redundant signed digit (RSD) arithmetic to avoid carry propagation and uses the minimum hardware per bit, i.e. one full…

Modular multiplication without trial division

- Mathematics, Computer Science
- 1985

A method for multiplying two integers modulo N while avoiding division by N, a representation of residue classes so as to speed modular multiplication without affecting the modular addition and subtraction algorithms.

Hardware speedups in long integer multiplication

- Computer ScienceSPAA '90
- 1990

It is demonstrated how a single host driving 3 differently configured PAM boards delivers RSA encryption and decryption faster than 200Kbits/sec for 512 bits keys, which beats the best currently working VLSI specially built for RSA by one order of magnitude.

A method for obtaining digital signatures and public-key cryptosystems

- Computer Science, MathematicsCACM
- 1983

An encryption method is presented with the novel property that publicly revealing an encryption key does not thereby reveal the corresponding decryption key. This has two important…

A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation

- Computer Science, MathematicsIEEE Trans. Computers
- 1992

A fast radix-4 modular multiplication hardware algorithm is proposed, efficient for modular exponentiation with a large modulus, used in public-key cryptosystems such as the RSA cryptos system and suitable for VLSI implementation.

Digit-Set Conversions: Generalizations and Application

- Computer Science, MathematicsIEEE Trans. Computers
- 1994

The problem of digit set conversion for fixed radix is investigated, and O(1) time algorithms for converting into redundant digit sets are generalized based on a very simple lemma, which provides a framework for all conversions into redundancies.

, Tony Denayer , and Paul G . A . Jespers . A New Carry - Free Division Algorithm and its A p plication to a Single - Chip 1024 b RSA Processor

- A Radix - 4 Modular Multiplic + tion Hardware Algorithm for Modular Exponentiation . IEEE lhanaactions on Computers , C - [ 9 ]

AMethod for Obtaining Digital Signatures and Public-key Cryptosystems

- Communications of the ACM,
- 1978