High radix implementation of Montgomery multipliers with CSA

@article{Sassaw2010HighRI,
  title={High radix implementation of Montgomery multipliers with CSA},
  author={Gashaw Sassaw and Carlos J. Jimenez and Manuel Valencia},
  journal={2010 International Conference on Microelectronics},
  year={2010},
  pages={315-318}
}
Modular multiplication is the key operation in systems based on public key encryption, both for RSA and elliptic curve (ECC) systems. High performance hardware implementations of RSA and ECC systems use the Montgomery algorithm for modular multiplication, since it allows results to be obtained without performing the division operation. The aim of this article is to explore various modified structures of the Montgomery algorithm for high speed implementation. We present the implementation of a… 

Figures and Tables from this paper

VLSI ARCHITECTURE FOR MONTGOMERY MODULAR MULTIPLICATION ALGORITHM BY USING PASTA ADDER
In data transmission applications, the widely used public-key cryptosystem is a simple and efficient Montgomery multiplication algorithm such that the low-cost and highperformance. In which includes
High-performance scalable architecture for modular multiplication using a new digit-serial computation
TLDR
A new scalable Montgomery modular multiplication architecture with variable-radix design with one clock cycle delay in data flow is proposed, which has area×time complexity and performance advantages compared to related algorithms/architectures.
High-Throughput Modular Multiplication and Exponentiation Algorithms Using Multibit-Scan–Multibit-Shift Technique
  • A. Rezai, P. Keshavarzi
  • Computer Science
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2015
TLDR
A new and efficient Montgomery modular multiplication architecture based on a new digit serial computation that relaxes the high-radix partial multiplication to a binary multiplication and performs several multiplications of consecutive zero bits in one clock cycle instead of several clock cycles is presented.
VLSI Implementation of High Performance Montgomery Modular Multiplication for Crypto Graphical Application
This paper proposes a simple and efficient Montgomery multiplication algorithm such that the low-cost and high-performance Montgomery modular multiplier can be implemented accordingly. Full -adder or
Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems
TLDR
This paper proposes an energy-efficient algorithm and its corresponding architecture that is capable of bypassing the superfluous carry-save addition and register write operations, leading to less energy consumption and higher throughput of Montgomery modular multipliers.
VLSI Implementation Of High Performance Montgomery Modular Multiplication For Crypto graphical Application
-The multiplier receives and outputs the data with binary representation and uses only one-level Carry Save Adder (CSA) to avoid the carry propagation at each addition operation. This CSA is also
A High Speed Montgomery Multiplier used in Security Applications
Security plays a major role in data transmission and reception. Providing high security is indispensable in communication systems. The RSA (Rivest–Shamir–Adleman) cryptosystem is used widely in
Low latency high throughput Montgomery modular multiplier for RSA cryptosystem
TLDR
A low latency and throughput efficient Montgomery modular multiplier that computes two subsequent quotients in parallel with carry-save addition is proposed and implemented on NEXYS4DDR and VIRTEX VII FPGA.
A Systolic Hardware Architecture of Montgomery Modular Multiplication for Public Key Cryptosystems
The Montgomery modular multiplication is mostly used in the field public-key cryptosystems. This work presents how to relax the data dependency in conventional word-based algorithms to increase the
High-Speed High-Throughput VLSI Architecture for RSA Montgomery Modular Multiplication with Efficient Format Conversion
TLDR
This paper proposes a fast and high-throughput Montgomery modular multiplier which employs an efficient format conversion method and shows that the proposed multiplier achieves significant speed and throughput improvement as compared to previous designs.
...
1
2
3
...

References

SHOWING 1-10 OF 24 REFERENCES
High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware
TLDR
This contribution proposes arithmetic architectures which are optimized for modern field programmable gate arrays (FPGAs) that perform modular exponentiation with very long integers, at the heart of many practical public-key algorithms such as RSA and discrete logarithm schemes.
Hardware Implementation of Improved Montgomery Modular Multiplication Algorithm
TLDR
A hardware implementation of modular multiplication coprocessor for both RSA and ECC Cryptosystems using a self-improvement Montgomery modular multiplication algorithm, which completes a modular multiplication with less clock cycles under the equivalent circumstance of the other designs.
High Speed RSA Implementation Based on Modified Booth's Technique and Montgomery's Multiplication for FPGA Platform
Rivest, Shamir and Adleman (RSA) encryption algorithm is one of the most widely used and popular public- key cryptosystem. The main step in this algorithm is modular exponentiation which can be done
Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm
TLDR
This paper has implemented two single-chip 1024-bit RSA processors based on the proposed architectures in 0.5-/spl mu/m SOG technology using Verilog-HDL and shown that each architecture contributes to speed improvement and area saving.
Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem
  • Jye-Jong Leu, A. Wu
  • Computer Science
    2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
  • 2000
TLDR
The 4 bit-digit-serial pipelined architecture to process RSA encryption/decryption in a more efficient way is proposed and the speed is approximately 1.7 times that of most RSA VLSI designs based on original Montgomery modular multiplication algorithm.
Modified Montgomery modular multiplication and RSA exponentiation techniques
Modified Montgomery multiplication and associated RSA modular exponentiation algorithms and circuit architectures are presented. These modified multipliers use carry save adders (CSAs) to perform
Three hardware implementations for the binary modular exponentiation: sequential, parallel and systolic
  • N. Nedjah, L. M. Mourelle
  • Computer Science
    Proceedings. 15th Symposium on Computer Architecture and High Performance Computing
  • 2003
TLDR
The characteristics of three architectures designed to implement modular exponentiation using the fast binary method are described: the first FPGA prototype has a sequential architecture, the second has a parallel architecture and the third has a systolic array-based architecture.
Analyzing and comparing Montgomery multiplication algorithms
TLDR
The operations involved in computing the Montgomery product are studied, several high-speed, space-efficient algorithms for computing MonPro(a, b), and their time and space requirements are described.
High speed radix-16 design of a scalable Montgomery multiplier
TLDR
An improved version of the Tenca-Todorov-Koc word based radix-8 Montgomery multiplier used for fast without adding any hardware, and adjusting the data-path to get shorter critical path, and requires half of FIFO memory.
An improved unified scalable radix-2 Montgomery multiplier
TLDR
An improved version of the Tenca-Koc unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision operands and half the queue memory requirement is described.
...
1
2
3
...