High quality Ta/sub 2/O/sub 5/ gate dielectrics with T/sub ox.eq/<10 /spl Aring/

@article{Luan1999HighQT,
  title={High quality Ta/sub 2/O/sub 5/ gate dielectrics with T/sub ox.eq/<10 /spl Aring/},
  author={H. Luan and S. H. Lee and C. H. Lee and S. C. Song and Y. L. Mao and Yuichiro Senzaki and D. Roberts and D. L. Kwong},
  journal={International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)},
  year={1999},
  pages={141-144}
}
High quality Ta/sub 2/O/sub 5/ gate stack with T/sub ox,eq/=9 /spl Aring/ (measured @ Vg=-2.5 V in strong accumulation without taking quantum mechanical effects into account) and the leakage current Jg=0.19 A/cm/sup 2/ @ Vg=-1.0 V has been achieved using NH/sub 3/-based interface layer, H/sub 2//O/sub 2/ post-deposition anneal and TiN diffusion barrier. The leakage current of Ta/sub 2/O/sub 5/ gate stack with NO interface layer is 10/sup 4/x lower than that of RTP SiO/sub 2/ with same T/sub ox… CONTINUE READING