High quality IP design using high-level synthesis design flow

@article{Zhu2016HighQI,
  title={High quality IP design using high-level synthesis design flow},
  author={Qiang Zhu and Masato Tatsuoka},
  journal={2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC)},
  year={2016},
  pages={212-217}
}
In this paper we will describe practical experiences about the use of high-level synthesis technologies to achieve higher performance, higher quality, and lower power for IP designs as compared to traditional RTL design. We will demonstrate how the introduction of three key techniques, interface-based design, architectural exploration and congestion-aware high-level synthesis, were utilized to achieve higher quality IP designs. In real application results, we will show significantly better QoR… CONTINUE READING

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Key Quantitative Results

  • In the case study, we showed that using HLS design flow we got average 35% better performance with up to 51% less power and up to 38% less area than hand-edited RTL for a DMAC IP.

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References

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