High precision alignment process for future 3D wafer bonding

Abstract

A new precision alignment process suitable for bonding distorted CMOS wafers is proposed. This process includes the following critical procedures: (A) correction of distorted wafers, (B) enhanced global alignment (EGA) for wafer-to-wafer (W2W) bonding, (C) contact between wafers with high alignment accuracy, and (D) clamping to maintain pre-bonding accuracy… (More)

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Cite this paper

@article{Sugaya2015HighPA, title={High precision alignment process for future 3D wafer bonding}, author={Isao Sugaya and Hajime Mitsuishi and Hidehiro Maeda and Masashi Okada and Kazuya Okamoto}, journal={2015 IEEE 65th Electronic Components and Technology Conference (ECTC)}, year={2015}, pages={348-353} }