High-power, high-efficiency digital polar doherty power amplifier for cellular applications in SOI CMOS

Abstract

This paper presents a Digital Doherty Power Amplifier (DDPA) with high back-off efficiency. The main and peaking amplifiers are implemented in 180 nm CMOS SOI as Digital Power Amplifiers (DPAs) with 10 bit amplitude control. The Doherty combiner is implemented using external matching components on a PCB, with lumped elements synthesized to provide equivalent characteristics of impedance inverter and offset-line. Phase adjustment between main and peaking DDPAs allows optimization of efficiency. CW measurements for the DDPA at 900 MHz correspond to 33.1 dBm peak power with 55.5% efficiency. This is highest reported output power for CMOS Doherty amplifiers. The efficiency at 6 dB back-off reaches 52.5%.

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Cite this paper

@article{Diddi2016HighpowerHD, title={High-power, high-efficiency digital polar doherty power amplifier for cellular applications in SOI CMOS}, author={Varish Diddi and Hamed Gheidi and James F. Buckwalter and Peter M. Asbeck}, journal={2016 IEEE Topical Conference on Power Amplifiers for Wireless and Radio Applications (PAWR)}, year={2016}, pages={18-20} }