High-performance low-energy STT MRAM based on balanced write scheme

@inproceedings{Lee2012HighperformanceLS,
  title={High-performance low-energy STT MRAM based on balanced write scheme},
  author={Dongsoo Lee and Sumeet Kumar Gupta and Kaushik Roy},
  booktitle={ISLPED},
  year={2012}
}
It is well known that high write time/energy in STT MRAM are aggravated by the asymmetry in write currents for '0'→'1' and '1'→'0' transitions. This asymmetry is primarily due to the source degeneration of the access transistor during write. In this work, we propose a design methodology which avoids the source degeneration of the access transistor, leading to balanced switching times for '0'→'1' and '1'→'0' transitions. This is achieved by using an additional (negative) bit-line voltage and… CONTINUE READING
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