High performance integrated Prolog processor IPP

@inproceedings{Abe1987HighPI,
  title={High performance integrated Prolog processor IPP},
  author={S. Abe and T. Bandoh and S. Yamaguchi and Ken-ichi Kurosawa and K. Kiriyama},
  booktitle={ISCA '87},
  year={1987}
}
To realize the highest performance possible for a sequential processor, and to realize utilization of a large amount of existing software, an integrated Prolog processor (IPP) and its optimized compiler are now being developed. A tagged architecture under constraints of a general purpose computer and a memory management strategy to achieve a high performance are discussed and then an IPP architecture is presented. Based on the Prolog instruction set, which is an extension of Warren's, the… Expand
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21 Citations
Background Citations
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Methods Citations
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21 Citations

Citation Type

Citation Type

Architecture of high performance integrated Prolog processor IPP
TLDR
A high speed integrated Prolog processor (IPP) which integrates the extended Warren's Prolog instructions, and its acceleration hardware into a 32-bit super-minicomputer, and a high cost/performance practical AI system can be realized. Expand
Performance evaluation of Integrated Prolog Processor IPP
TLDR
The main extensions of the IPP are to select as the optimal argument the variable that exists in a type checking predicate and to eliminate type checking from a clause code if such a predicate exists; and to detect unification failure as early as possible, and to resolve register conflicts. Expand
Prolog on a RISC: Implementation and evaluation
TLDR
The performances obtained on a 20 MHz clocked MIPS are close to the performances of WAM-based Prolog machines. Expand
Evaluation of memory system for integrated Prolog processor IPP
TLDR
An optimal memory system to realize a high performance integrated Prolog processor, the IPP is discussed, and it is concluded that the advanced store-through cache is best suited to theIPP. Expand
A pipelined architecture for logic programming with a complex but single-cycle instruction set
  • J. W. Mills
  • Computer Science
  • [Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence
  • 1989
An architecture that executes logic programs using fewer instruction cycles than hardware implementations of the Warren Abstract Machine or the Berkeley SPUR augmented with a Prolog coprocessor is… Expand
A pipelined microprocessor for logic programming languages
TLDR
The architecture of a pipelined microprocessor for logic programming languages is presented, and the hardware architecture of PU is described, focusing on its data typing and dereference mechanisms. Expand
Design and performance measurements of a parallel machine for the unification algorithm
TLDR
A parallel unification machine is proposed for speeding up the unification algorithm and the simulation results as well as performance comparison with a serial unification coprocessor are presented. Expand
An Extended Prolog Instruction Set for RISC Processors
TLDR
Extensions of a RISC processors’s instruction set are presented to enable a simplified and more efficient implementation of Prolog. Expand
Implementing a parallel PROLOG interpreter by using OCCAM and transputers
Abstract occam is a message-based parallel language that allows programs to be written with a large number of living processes. The transputer, which supports occam very efficiently, allows parallel… Expand
A Performance Comparison between PLM and a M68020 PROLOG Processor
Logic programming implementation / application issues : Compiler construction / optimizations, Efficient operator precedence (bottom-up) parsers, Native code backend specifications, Multi-threaded… Expand
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References

SHOWING 1-4 OF 4 REFERENCES
An Optimizing Prolog Compiler
TLDR
This paper reports on the experiment on Prolog compiler technology and introduces some declarative extensions, which are compatible with Prolog and powerful enough to produce efficient code. Expand
Performance studies of a Prolog machine architecture
TLDR
This paper descr ibes a special purpose processor, the PLM, which the authors have designed for high pe r fo rmance execu t ion of Prolog programs, and some aspects of its imp lemen ta t ion. Expand
A static analysis of prolog programs
TLDR
This document summarizes the results of this static analysis of Prolog programs, done using a program written in Prolog, which collects data from test programs. Expand
Design of a high-speed Prolog machine (HPM)
This paper d e s c r i b e s a High-speed Prolog Machine (HIM) a r c h i t e c t u r e and i t s hardware s t r u c t u r e , which are developed as a product of F i f t h Genera t ion Computer… Expand