High performance integrated Prolog processor IPP
@inproceedings{Abe1987HighPI, title={High performance integrated Prolog processor IPP}, author={Shigeo Abe and Tadaaki Bandoh and Shinichiro Yamaguchi and Ken-ichi Kurosawa and Kaori Kiriyama}, booktitle={ISCA '87}, year={1987} }
To realize the highest performance possible for a sequential processor, and to realize utilization of a large amount of existing software, an integrated Prolog processor (IPP) and its optimized compiler are now being developed.
A tagged architecture under constraints of a general purpose computer and a memory management strategy to achieve a high performance are discussed and then an IPP architecture is presented. Based on the Prolog instruction set, which is an extension of Warren's, the…
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Architecture of high performance integrated Prolog processor IPP
- Computer ScienceFJCC
- 1987
A high speed integrated Prolog processor (IPP) which integrates the extended Warren's Prolog instructions, and its acceleration hardware into a 32-bit super-minicomputer, and a high cost/performance practical AI system can be realized.
Performance evaluation of Integrated Prolog Processor IPP
- Computer ScienceProceedings of the International Workshop on Artificial Intelligence for Industrial Applications
- 1988
The main extensions of the IPP are to select as the optimal argument the variable that exists in a type checking predicate and to eliminate type checking from a clause code if such a predicate exists; and to detect unification failure as early as possible, and to resolve register conflicts.
Evaluation Of Memory System For Integrated Prolog Processor IPP
- Computer ScienceThe 16th Annual International Symposium on Computer Architecture
- 1989
An optimal memory system to realize a high performance integrated Prolog processor, the IPP is discussed, and it is concluded that the advanced store-through cache is best suited to theIPP.
A pipelined architecture for logic programming with a complex but single-cycle instruction set
- Computer Science[Proceedings 1989] IEEE International Workshop on Tools for Artificial Intelligence
- 1989
An architecture that executes logic programs using fewer instruction cycles than hardware implementations of the Warren Abstract Machine or the Berkeley SPUR augmented with a Prolog coprocessor is…
A pipelined microprocessor for logic programming languages
- Computer ScienceProceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors
- 1990
The architecture of a pipelined microprocessor for logic programming languages is presented, and the hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.
Design and performance measurements of a parallel machine for the unification algorithm
- Computer ScienceMICRO 22
- 1989
A parallel unification machine is proposed for speeding up the unification algorithm and the simulation results as well as performance comparison with a serial unification coprocessor are presented.
An Extended Prolog Instruction Set for RISC Processors
- Computer Science
- 1991
Extensions of a RISC processors’s instruction set are presented to enable a simplified and more efficient implementation of Prolog.
Implementing a parallel PROLOG interpreter by using OCCAM and transputers
- Computer ScienceMicroprocess. Microsystems
- 1989
A Performance Comparison between PLM and a M68020 PROLOG Processor
- Computer ScienceICLP
- 1987
Logic programming implementation / application issues : Compiler construction / optimizations, Efficient operator precedence (bottom-up) parsers, Native code backend specifications, Multi-threaded…
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