High-performance gate sizing with a signoff timer

@article{Kahng2013HighperformanceGS,
  title={High-performance gate sizing with a signoff timer},
  author={Andrew B. Kahng and Seokhyeong Kang and Hyein Lee and Igor L. Markov and Pankit Thapar},
  journal={2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)},
  year={2013},
  pages={450-457}
}
Process and device scaling in late-CMOS technologies highlight leakage power as a critical challenge for the semiconductor industry. Careful gate sizing and Vth-swapping can reduce leakage, but prior optimizations based on convex or dynamic programming (i) are often based on unrealistic assumptions about circuit delay and slew propagation, (ii) fail to handle practical design rules such as transition time or load upper bounds, and (iii) do not scale well to input complexities when full… CONTINUE READING
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