High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

@article{Singh2006HighperformanceFD,
  title={High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices},
  author={N. Singh and A. Agarwal and L. K. Bera and T. Y. Liow and R. Yang and S. C. Rustagi and C. Tung and R. Kumar and G. Q. Lo and N. Balasubramanian and D. Kwong},
  journal={IEEE Electron Device Letters},
  year={2006},
  volume={27},
  pages={383-386}
}
  • N. Singh, A. Agarwal, +8 authors D. Kwong
  • Published 2006
  • Chemistry
  • IEEE Electron Device Letters
  • This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub… CONTINUE READING
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