High performance circuit techniques for dynamic OR gates


In this paper, two methods for high fan-in dynamic OR gates are proposed. The methods are called high-speed low-swing OR gate (HSLS-OR) and low-power selective evaluate OR gate (LPSE-OR). HSLS-OR contains separate parallel NMOS logic trees in which one controls the evaluation phase of the other ones. This leads to a low voltage swing in the dynamic… (More)
DOI: 10.1109/ISCAS.2006.1693421

3 Figures and Tables


  • Presentations referencing similar topics