High-performance and Low-power Challenges for Sub-7 Onm Microprocessor Circuits

@inproceedings{Ram2004HighperformanceAL,
  title={High-performance and Low-power Challenges for Sub-7 Onm Microprocessor Circuits},
  author={Preetha. Ram and Sundar R. Krishnamurthy and Atila Alvandpour},
  year={2004}
}
CMOS technology scaling is becoming difficult beyond 70nm node, raising new design challenges for highperformance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described. 

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