High performance VLSI architecture for 3-D discrete wavelet transform


This paper presents a high-speed memory efficient VLSI architecture for three dimensional (3-D) discrete wavelet transform. A major strength of the proposed architecture lies in reducing the number and period of clock cycles for the computation of wavelet transform. This five stage pipelined architecture shares the partial load of the next stage with the… (More)
DOI: 10.1109/VLSID.2014.66


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