High-performance FPGA implementation of DES using a novel method for implementing the key schedule

@inproceedings{McLoone2003HighperformanceFI,
  title={High-performance FPGA implementation of DES using a novel method for implementing the key schedule},
  author={M{\'a}ire McLoone and John V. McCanny},
  year={2003}
}
A generic, parameterisable key scheduling core is presented, which can be utilised in pipelinable private-key encryption algorithms. The data encryption standard (DES) algorithm, which lends itself readily to pipelining, is utilised to exemplify this novel key scheduling method and the broader applicability of the method to other encryption algorithms is illustrated. The DES design is implemented on Xilinx Virtex FPGA technology. Utilising the novel method, a 16-stage pipelined DES design is… 
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