High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs
@article{Takato1988HighPC, title={High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs}, author={Hiroshi Takato and Kazumasa Sunouchi and Naoto Okabe and Akihiro Nitayama and Katsuhiko Hieda and Fumio Horiguchi and Fujio Masuoka}, journal={Technical Digest., International Electron Devices Meeting}, year={1988}, pages={222-225} }
A novel transistor with compact structure has been developed for MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors. The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These features are due to the unique structure, which results in greater…
89 Citations
Multi-pillar surrounding gate transistor (M-SGT) for compact and high-speed circuits
- Engineering
- 1991
The M-SGT has a three-dimensional structure, which consists of the source, gate, and drain arranged vertically. The gate electrode surrounds the crowded multipillar silicon islands. Because all the…
Vertical MOS Transistors with 70nm Channel Length
- EngineeringESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference
- 1995
Vertical nMOS transistors with channel lengths down to 70nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography.…
"Depletion isolation effect" of surrounding gate transistors
- Engineering
- 1997
Sub-half-micron surrounding gate transistors (SGTs) were fabricated and their current-voltage (I-V) characteristics were investigated. Even in a SGT whose Si pillar is not fully depleted (e.g., 0.6…
A Compact Space and Efficient Drain Current Design for Multipillar Vertical MOSFETs
- EngineeringIEEE Transactions on Electron Devices
- 2010
In the vertical MOSFET, due to its device structure, the bottom of its silicon pillar has a certain resistance because there is a diffused silicon wiring area in the bottom. Thereby, this resistance…
Silicon-Nanowire MOSFETs
- Engineering
- 2008
We present vertical Gate-All-Around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50:1) vertical nanowires with…
Gate-All-Around Technology for Harsh Environment Applications
- Engineering
- 1999
Gate-Ail-Around (GAA) transistors are thin, fully depleted SOI MOSFETs with a double gate structure. When used at high temperature GAA devices present low leakage current, minimal threshold voltage…
Impact of the vertical SOI 'DELTA' structure on planar device technology
- Engineering
- 1991
A fully depleted lean channel transistor (DELTA) with its gate incorporated into a new vertical ultrathin silicon-on-insulator (SOI) structure is presented. In the deep-submicrometer region,…
CMOS compatible Gate-All-Around Vertical silicon-nanowire MOSFETs
- EngineeringESSDERC 2008 - 38th European Solid-State Device Research Conference
- 2008
We present vertical gate-all-around (GAA) silicon nanowire transistors on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50:1) vertical nanowires with…
Design of Double Gate Vertical MOSFET using Silicon On Insulator (SOI) Technology
- Engineering
- 2012
Application of symmetric double gate vertical metal oxide semiconductorfield effect transistors (MOSFETs) is hindered by the parasitic overlapcapacitance associated with their layout, which is…
Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET
- EngineeringIEEE Electron Device Letters
- 2008
This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with…