• DOI:10.1109/IEDM.1988.32796
• Corpus ID: 114148274

High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

@article{Takato1988HighPC,
  title={High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs},
  author={Hiroshi Takato and Kazumasa Sunouchi and Naoto Okabe and Akihiro Nitayama and Katsuhiko Hieda and Fumio Horiguchi and Fujio Masuoka},
  journal={Technical Digest., International Electron Devices Meeting},
  year={1988},
  pages={222-225}
}

• H. Takato, K. Sunouchi, +4 authors F. Masuoka
• Published 11 December 1988
• Engineering
• Technical Digest., International Electron Devices Meeting

A novel transistor with compact structure has been developed for MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors. The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These features are due to the unique structure, which results in greater gate controllability and in electric field relaxation at the drain edge.<<ETX>>