High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs

  title={High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs},
  author={H. Takato and K. Sunouchi and N. Okabe and A. Nitayama and K. Hieda and F. Horiguchi and F. Masuoka},
  journal={Technical Digest., International Electron Devices Meeting},
  • H. Takato, K. Sunouchi, +4 authors F. Masuoka
  • Published 1988
  • Engineering
  • Technical Digest., International Electron Devices Meeting
  • A novel transistor with compact structure has been developed for MOS devices. This transistor, whose gate electrode surrounds the pillar silicon island, reduces the occupied area for all kinds of circuits. For example, the occupied area of a CMOS inverter can be shrunk to 50% of that using planar transistors. The other advantages are steep cutoff characteristics, very small substrate bias effects, and high reliability. These features are due to the unique structure, which results in greater… CONTINUE READING
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