High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs

@article{Goto2003HighP2,
  title={High performance 25 nm gate CMOSFETs for 65 nm node high speed MPUs},
  author={K. Goto and Y. Tagawa and H. Ohta and H. Morioka and Sergey Pidin and Y. Momiyama and H. Kokura and S. Inagaki and Naoyoshi Tamura and Mitsuaki Hori and T. Mori and Masataka Kase and K. Hashimoto and M. Kojima and T. Sugii},
  journal={IEEE International Electron Devices Meeting 2003},
  year={2003},
  pages={27.1.1-27.1.4}
}
  • K. Goto, Y. Tagawa, +12 authors T. Sugii
  • Published in IEEE International Electron Devices Meeting 2003
  • DOI:10.1109/iedm.2003.1269358
Aggressively scaled 25 nm gate CMOSFETs for the 65 nm node are reported. We successfully improved the short channel effect while keeping a high drive current by using total process controls (SW, offset-spacer, extension, halo, mechanical stress, etc.). Both mobility in nMOS and NBTI in pMOS are improved by combination of low temperature annealing and oxynitride gate oxide with low nitrogen concentration. High drive currents of 840/1010 /spl mu/A//spl mu/m and CV/I values of 0.54/0.60 psec with… CONTINUE READING

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