High-level symbolic simulation for automatic model extraction

@article{Ouchet2009HighlevelSS,
  title={High-level symbolic simulation for automatic model extraction},
  author={Florent Ouchet and Dominique Borrione and Katell Morin-Allory and Laurence Pierre},
  journal={2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems},
  year={2009},
  pages={218-221}
}
This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types. 

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