High-level design verification using Taylor Expansion Diagrams: first results

@article{Kalla2002HighlevelDV,
  title={High-level design verification using Taylor Expansion Diagrams: first results},
  author={Priyank Kalla and Maciej J. Ciesielski and Emmanuel Boutillon and Eric Martin},
  journal={Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.},
  year={2002},
  pages={13-17}
}
Recently a theory of a compact, canonical representation for arithmetic expressions, called Taylor Expansion Diagram (TED) has been proposed. This representation, based on a novel, non-binary decomposition principle, raises a level of design abstraction from bits to bit vectors and words, thus facilitating the verification of behavioral and RTL specifications of arithmetic designs. This paper presents the first practical results of using TED in the context of high-level design representation… CONTINUE READING

Citations

Publications citing this paper.
SHOWING 1-8 OF 8 CITATIONS

Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams

  • 2005 IEEE International Symposium on Circuits and Systems
  • 2005
VIEW 7 EXCERPTS
CITES BACKGROUND
HIGHLY INFLUENCED

Sharing Methods of Multi-objective Functions Based on TED

  • First International Multi-Symposiums on Computer and Computational Sciences (IMSCCS'06)
  • 2006
VIEW 1 EXCERPT
CITES BACKGROUND

Controlling the memory during manipulation of word-level decision diagrams

  • 35th International Symposium on Multiple-Valued Logic (ISMVL'05)
  • 2005
VIEW 1 EXCERPT
CITES BACKGROUND

TED+: a data structure for microprocessor verification

  • Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.
  • 2005
VIEW 3 EXCERPTS
CITES METHODS & BACKGROUND

Algorithms for Taylor expansion diagrams [IC design/verification applications]

  • Proceedings. 34th International Symposium on Multiple-Valued Logic
  • 2004
VIEW 1 EXCERPT
CITES RESULTS