High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

@article{Jadidi2011HighenduranceAP,
  title={High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement},
  author={Amin Jadidi and Mohammad Arjomand and Hamid Sarbazi-Azad},
  journal={IEEE/ACM International Symposium on Low Power Electronics and Design},
  year={2011},
  pages={79-84}
}
In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive… CONTINUE READING
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