High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique

Abstract

This paper presents an efficient low power protection technique for thin gate oxide of DMOS transistors. By connecting a capacitive divider structure to the floating gate node of a DMOS transistor, its effective gate oxide thickness is increased, and a protection from breakdown due to high voltages (HV) applied to its gate is achieved. Several HV circuits… (More)
DOI: 10.1109/ISCAS.2007.378227

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Cite this paper

@article{Chebli2007HighVoltageDI, title={High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique}, author={Robert Chebli and Mohamad Sawan and Yvon Savaria and Kamal El-Sankary}, journal={2007 IEEE International Symposium on Circuits and Systems}, year={2007}, pages={3343-3346} }