High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree

  title={High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree},
  author={Yuan-Ho Chen and Tsin-Yuan Chang and Chung-Yi Li},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
In this brief, by operating the shifting and addition in parallel, an error-compensated adder-tree (ECAT) is proposed to deal with the truncation errors and to achieve low-error and high-throughput discrete cosine transform (DCT) design. Instead of the 12 bits used in previous works, 9-bit distributed arithmetic-precision is chosen for this work so as to meet peak-signal-to-noise-ratio (PSNR) requirements. Thus, an area-efficient DCT core is implemented to achieve 1 Gpels/s throughput rate with… CONTINUE READING
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A 250 MHz optimized distributed architecture of 2D 8 8 DCT

  • C. Peng, X. Cao, D. Yu, X. Zhang
  • Proc. Int. Conf. ASIC, 2007, pp. 189–192.
  • 2007
Highly Influential
8 Excerpts

A 100-MHz 2-D discrete cosine transform core processor

  • S. Uramoto, Y. Inoue, +4 authors M. Yoshimoto
  • IEEE J. Solid-State Circuits, vol. 27, no. 4, pp…
  • 1992
Highly Influential
4 Excerpts

A high - speed 2 - D transform architecture with unique kernel for multi - standard video applications , ” in

  • F. E. Guibaly Kidambi, A. Antonious
  • Proc . IEEE Int . Symp . Circuits Syst .
  • 2008

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